Programmable digital memories generally are either nonvolatile or volatile. A nonvolatile memory is able to store information for a period of time or indefinitely, with or without electrical power being supplied to it, but such memories tend also to be relatively slow, and, in particular, often require long write times. Volatile memories are unable to continue to store information unless electrical power is continuously supplied to them, but are often much faster than nonvolatile memories.
One type of volatile memory is known as RAM or random access memory. RAMs are used in a variety of digital equipment for read-write memory, where speed and accuracy are both important. RAMs are easily written to and can provide very rapid access to stored data.
SRAMs, or static random access memories, require more silicon area per memory cell than do DRAMs, or dynamic random access memories. Additionally, SRAMs typically consume more electrical power per bit than do DRAMs. As a result, SRAMs are typically used in situations where their increased operating speed provides critical system performance advantages over DRAMs. A typical SRAM memory cell includes between four and six FETs, with two of the FETs forming bit line transfer devices and two to four FETs coupled to provide cross-coupled inverters forming a latch.
During a memory write operation, the bit line transfer devices are turned ON and the cross-coupled inverters forming the SRAM memory cell are driven to one of two possible logical states, thereby writing data to the SRAM memory cell. The bit line transfer devices are then turned OFF and the cross-coupled inverters maintain the logical states that they were placed in during the memory write operation.
During a memory read operation, the bit line transfer devices are turned ON, and the outputs of the cross-coupled inverters forming the SRAM memory cell are coupled to a sensing circuit that reads the logical state of the cross-coupled inverters. At the conclusion of the memory read operation, the bit line transfer devices are turned OFF, and the SRAM memory cell continues to store the data previously written to the SRAM memory cell.
The cross-coupled inverters forming the SRAM memory cell typically have no provision for storing data when no electrical power is being supplied to the SRAM. As a result, data stored in the SRAM are lost when power supply failures occur.
One prior art approach for providing a nonvolatile memory function in an SRAM stores data from the SRAM memory cell in an associated flash memory cell that is built into the SRAM memory cell. When a power supply anomaly is detected in the SRAM power supply, all word lines to the SRAM are turned OFF, and an internal high voltage power supply is turned ON. The internal high voltage power supply provides an elevated voltage such as 15 volts. When the internal high voltage power supply has equilibrated, shadow memory access FETs are turned ON and the flash memory cell stores the data that is stored in their associated SRAM memory cell. The flash memory cells then maintain the stored data, whether the SRAM power supply continues to operate or not.
Following return of the SRAM power supply to a normal condition, the word lines are turned OFF and the shadow memory access FETs are turned ON. The data stored in the flash memory cells are read back into the associated SRAM memory cells, restoring the data that were stored in the SRAM before the SRAM power supply exhibited the anomaly. The SRAM is then returned to normal operation.
Disadvantages to this approach include the need to be able to generate the internal high voltage and the need for circuitry to support the flash memory cell operation. Additionally, the flash memory cell itself requires additional processing steps in the manufacture of the SRAM shadow memory.